The present invention relates to a design method and design system for a semiconductor integrated circuit using standard cells. More specifically, the present invention relates to a design method and design system for a semiconductor integrated circuit which can reduce a device placement area through sharing of part of standard cell regions.
In recent years, automatic placement and automatic wiring using standard cells have been performed in the layout design of semiconductor integrated circuits in order to achieve efficient layout design. In a design method using standard cells, cells are automatically placed using a computer, which proves advantageous since a design can be executed in a short time. However, in conventional automatic design methods using standard cells, the cells are simply laid out in such a manner that there are no overlapping standard cells, and this leads to the problem of increased device placement area. In a semiconductor integrated circuit process, it is necessary to execute a design in a short time, and also make the device placement area small. Therefore, the major challenge for the conventional design methods using standard cells is to achieve a reduction in device placement area.
A conventional automatic design method using standard cells will now be described. It is assumed that a circuit as shown in FIG. 7, for example, is designed using standard cells. Circuit information of a standard cell contains information on the constituent circuits and their connections. Circuit information 701 and 702 each represent an inverter, and circuit information 703 represents a transfer gate. Circuit information 704 to 713 are information on their connections. In the following description, these circuit information will be represented as, for example, the inverter 701 and the transfer gate 703 for the simplicity of description.
In a design method using standard cells, an individual standard cell is prepared in advance with respect to each of basic circuits (also referred to as “cells”). An inverter and a transfer gate are prepared as the basic circuits constituting the circuit shown in FIG. 7. These inverter and transfer gate are represented as an inverter 301 and a transfer gate 302 in FIG. 3. FIG. 4 shows standard cells 401 and 403 corresponding to the inverter 301 and the transfer gate 302, respectively.
The standard cells prepared in this way are placed in accordance with the circuit information of FIG. 7. As shown in FIG. 8, the inverter 701, the inverter 702, and the transfer gate 703 are placed as standard cells 801, 802, and 803, respectively. In this case, the device placement area is at least equal to the sum total of the areas of the placed standard cells, and cannot be reduced any further. Since the resulting device placement area is large as described above, contrivances have been made to reduce the device placement area. Examples of related art techniques aimed at reducing the device placement area include those described in the patent documents below.
Japanese Unexamined Patent Application Publication No. 2001-351981 (which is referred to as patent document 1) discloses a technique according to which, with the edge portion of a standard cell being an electric potential system that does not fluctuate, such as a power supply voltage (VDD, VSS), this is constituted by a source (diffusion layer), and a cell designed in a given configuration is used. When such standard cells are placed, and the edge portions of adjacent standard cells are identical, the edge portions of the adjacent standard cells are shared with each other. That is, under the restricted condition with the edge portion of a standard cell being a power supply voltage system (VDD, VSS), the cells are placed after deleting the redundant edge portions, thereby reducing the device placement area. Further, according to the technique described in the patent document 1, the determination as to whether the cells can be placed while deleting their redundant portions is made solely on the basis of information on the configuration of the edge portions of standard cells, and there is no mechanism provided for electric potential checking. Accordingly, the range of applicable standard cell configurations is limited, making the application of the technique to most standard cells difficult.
For example, referring to FIG. 18, a total of five kinds of standard cells are considered here, including standard cells 1801, 1802, and 1803 used in an embodiment of the present invention that will be described later, and standard cells 1804 and 1805 of a unique structure suited to the technique described in the patent document 1. The standard cells 1801 to 1803 are of a cell structure that takes into consideration the fact that wire connection can be smoothly performed during the process of automatic wiring after the placement of cells by ensuring that a wiring pattern be always inserted in the port (terminal) portion of a cell as indicated at 1806. On the other hand, with the standard cells 1804 and 1805, automatic wiring after the placement of cells is difficult because no wiring pattern exists in the port portion of the cells.
It is assumed that, on the basis of the above, the technique described in the patent document 1 is applied to all of these standard cells. In this case, there is the possibility of a reduction in area due to the deletion of redundant portions only in the case where the edge portion of a cell consists solely of a source (diffusion layer) with a completely fixed potential, as in the region of the standard cell 1804 indicated at 1808. In all of the other standard cells, however, at least one region where the potential fluctuates, that is, a pattern having a potential other than the source, is included in the edge portion, as indicated at 1806 in the standard cell 1801, for example. Therefore, the device placement area is not reduced at all even when the technique according to the patent document 1 is applied.
Patent document 2 (Japanese Unexamined Patent Application Publication No. 2004-252717) discloses providing a high-speed cell having a first cell region, and a low-leak cell having a second region obtained by enlarging the high-speed cell. Cells of the same kind are set as those of the first cell region, thereby realizing efficient layout. Patent document 3 (Japanese Unexamined Patent Application Publication No. 04-144153) and patent document 4 (Japanese Unexamined Patent Application Publication No. 01-239871) each disclose a technique of imparting attributes to the end portion, edge, or boundary between cells, thereby allowing sharing of the end portions of the cells. However, it cannot be said that even the above techniques disclosed in these patent documents sufficiently attain the object of reducing the device placement area, and a better solution is being desired.